A network device, such as a switch or router, may include a network processor that facilitates transmission of data, such as cells or frames, into and out of the network device. Such a network processor may store information in memory, in one or more control structures (e.g., control blocks), corresponding to data transmitted to the network processor.
A data coherency problem may arise within a network processor when multiple components of the network processor attempt to modify the same control structure at nearly the same instant in time or during an overlapping time period. For example, one component of a network processor may attempt to modify a control structure in a memory while another component is modifying the same control structure in the memory.
Some network processors use a bus protocol that prevents a component from modifying a control structure (e.g., by locking access to the control structure) while another component that is coupled to the same bus is modifying the control structure. Alternatively, some network processors use a bus protocol that employs snooping methods to determine whether a component that is coupled to a bus is modifying the control structure. If a component is modifying the control structure, other components must wait until the component has completed its modifications. However, this approach only works on certain bus protocols. While effective, bus protocol and/or snooping techniques tend to be complex, process intensive and expensive to implement, and may be unavailable (e.g., in an existing processor that lacks such features). Accordingly a need exists for improved methods and apparatus for maintaining data coherency in a network processor.